The present claimed invention generally relates to semiconductors. More specifically, the present claimed invention relates to a method of forming a semiconductor device.
Various techniques known in the art can be used to fabricate a semiconductor device such as an integrated circuit or processor. In general, these techniques typically involve applying a layer of material to an underlying substrate or over a preceding layer, and then selectively removing the material using an etch process. Using these techniques, the components of a semiconductor device, perhaps comprising different types of material, can be accurately formed and placed.
One type of component used by semiconductor devices is an isolation device. An isolation device, in general, includes a stacked gate isolated from an adjacent stacked gate by a shallow trench. The isolation device also typically includes a spacer formed on the sidewalls of the stacked gate.
Prior Art FIGS. 1A through 1F illustrate a prior art process for forming spacers in an isolation device. For simplicity of discussion, the process is described for a single spacer 50 (FIG. 1F) formed on the sidewall 11 of a stacked gate 10 adjacent to a shallow trench 12. Shallow trench 12 is filled with a material such as high density plasma (HDP) oxide.
Referring first to FIG. 1A, a residual oxide layer 14 (e.g., silicon dioxide, SiO2) is formed over stacked gate 10 (including sidewall 11) and shallow trench 12. The residual oxide layer 14 is formed during annealing of the silicon. Usually, the residual oxide layer 14 includes a pre-implant oxide layer and a layer of oxide grown by a gate anti-reflective coating (GARC) anneal. Typically, the pre-implant oxide layer is approximately 50 to 75 Angstroms (xc3x85) in thickness, and the oxide layer grown by the GARC anneal is approximately 95 xc3x85 in thickness. However, the total thickness of the residual oxide layer 14 is actually something less than the sum of the thicknesses of the pre-implant oxide layer and the oxide layer grown by the GARC anneal. A typical residual oxide layer 14 is approximately 100 xc3x85 in depth, although it may be less.
With reference to FIG. 1B, a liner layer 16 of a first material, typically TEOS (tetraethylorthosilicate), is deposited over stacked gate 10 (including sidewall 11) and shallow trench 12. Liner layer 16 typically has a thickness of approximately 150 xc3x85.
Next referring to FIG. 1C, a layer 18 of a second material, typically nitride, is deposited over the liner layer 16. Referring now to FIG. 1D, an etch of layers 16 and 18 is performed, removing the nitride and essentially all of the TEOS from the horizontal surfaces of the isolation device; however, a thin layer of TEOS typically remains on the surface 20 over shallow trench 12. Also, a layer 16 of TEOS and a layer 18 of nitride also remain on the sidewall of stacked gate 10. The residual oxide layer 14, underlying the other layers, also remains.
With reference to FIG. 1E, a layer 22 of material, typically nitride, is deposited over the remaining portions of layers 16 and 18. Referring now to FIG. 1F, an etch of layer 22 is performed to remove layer 22 from the horizontal surfaces of the isolation device and to form a spacer 50 having a prescribed (design) thickness T1. Spacer 50 is thus formed of layers 16, 18 and 22 using a process that includes two etches. The residual oxide layer 14, underlying the other layers, also is present along sidewall 11.
A problem with the process illustrated by FIGS. 1A through 1F is that, during the second etch, relatively significant gouging of the HDP oxide in shallow trench 12 often occurs. The liner layer 16 is reduced to a thin layer, or effectively removed, during the first etch. Any remaining portion of layer 16 is not sufficiently thick to withstand the second etch and serve as a protective layer for the shallow trench 12 for the duration of the second etch. Consequently, shallow trench 12 is exposed during the second etch, allowing the HDP oxide to be gouged by the etch.
As a result of the gouging, isolation issues may be introduced, reducing the effectiveness of the isolation device. If these isolation issues are not detected or corrected, the performance of the semiconductor device may also be affected. Detection and correction of the gouging can reduce the yield (throughput) of the fabrication process and increase the unit cost of the semiconductor device.
Accordingly, what is needed is a method and/or system that can be used to form spacers in an isolation device, but without gouging the shallow trench filler material. The present invention provides a novel solution to this need.
Embodiments of the present invention provide a method and system thereof that can be used to form spacers in an isolation device, but without gouging the shallow trench filler material.
In one embodiment, an oxide layer is produced on a sidewall of a stacked gate and over a shallow trench adjacent to the stacked gate. The thickness of the oxide layer is sufficient to withstand a subsequent etch. A first layer of material is deposited over the oxide layer. In a first etch, the first layer is reduced to a first thickness along the sidewall. Because the oxide layer has a depth sufficient to withstand the first etch, the oxide layer serves as a protective layer for the shallow trench during the first etch. Accordingly, a protective liner layer does not need to be deposited in addition to the oxide layer.
In one embodiment, a second layer is deposited to a second thickness over the first layer subsequent to the first etch. A third layer is deposited over the second layer. In a second etch, the third layer is reduced to a third thickness along the sidewall. During the second etch, the second layer serves as a protective layer for the shallow trench. In the present embodiment, the first, second and third layers in combination form a spacer having a thickness corresponding to the first, second and third thicknesses.
In one embodiment, the first layer comprises nitride. In one embodiment, the second layer comprises TEOS (tetraethylorthosilicate). In another embodiment, the third layer comprises nitride. In yet another embodiment, the shallow trench is substantially filled with material comprising high density plasma (HDP) oxide. In another embodiment, the oxide layer is a residual oxide layer comprising a pre-implant oxide layer and an oxide layer grown by a gate anti-reflective coating (GARC) anneal. In one embodiment, the depth of the residual oxide layer is between approximately 150 and 180 Angstroms.
In its various embodiments, the present invention protects the shallow trench (e.g., the HDP oxide filler material) from gouging during etching, particularly during the second etch. This aspect of the present invention is especially beneficial as the length (in time) of the second etch is increased in order to remove nitride stringers at the core-periphery interface.